Often in digital and digital-analog integrated circuits it is necessary to include a finite state machine that operates as an interface between the external circuitry (user) and one or more internal functional circuits, such as counters, microcontrollers, converters, and the like. Such a structure must be able to update its internal state to give a precise indication of the working condition of the device at every instant, and should also be able to receive user commands and communicate the information (if so required) to certain functional circuits, wait for their response, run embedded algorithms, signal the end of these algorithms, etc.
Often, the interface performs a true handshake among the external circuits and one or more internal circuits. The interface assumes a basic role and any malfunctions, even in just one of the tasks that it carries out, may in some cases cause an interruption of communications, and consequently, require a hardware reset of the whole integrated circuit for a new start from the initial conditions.
The specifications to be satisfied by this type of structure may be subdivided in two categories:
1) The interface may modify its own state only upon a user clock pulse (CLK), and in this phase, it will carry out its own evaluation based on the values present at the external inputs as well as on signals coming from the internal circuits with which it interfaces. In this case, the interface acts only upon reception of a user command taking into account all information provided to it. Its functioning is akin to the work of an employee who acts on command from a single boss (external circuits), taking into account what his colleagues (internal circuits) have communicated to him.
2) The interface may modify its state upon commands coming from one or several internal circuits (from peer circuits). In this case, its functioning is akin to that of an employee that carries out tasks assigned to him from time to time by two or more bosses, without any allowance for missing performance of any of the received commands, unless recognizably useless.
Typically, in such circuits, operation requests coming from external circuits are of various kinds and rather complex and are issued in the form of a bit sequence, the combinations of which must be suitably encoded and correspond, in general, to tens of possible commands. On the contrary, the handshake with any of the relevant internal circuits takes place through the communication of just a few bits (often a single bit or flag) that signals an acknowledge or an end operation.
The considerations that will be made in the following description and the invention relate to interface structures belonging to the second category. The specifications of these interface structures are relatively more burdening and complex than those of an interface structure belonging to the first category.
The relative complexity of the design of these interfaces of the second category derives from the fact that the specification of these structures does not allow for a straightforward identification of an appropriate design of a suitable state machine according to classic design rules established in the literature. In fact, various methods for the implementation of synchronous machines may be found in the literature, but they are all based on the assumption that they work with a single clock and with a single reset.
Conventionally, the variety of commands is peculiar of and attributed to external commands, while in contrast the internal circuits communicate among them through simple acknowledge signals. According to the designs so far practiced, the state machine (also referred to as SM throughout the description) is considered as a synchronous machine that receives its clock from external circuits and manages the interaction with the internal circuits in an asynchronous mode by resetting the bistable state circuits (FF) according to conditions based on information coming from the internal circuits.
Assuming that, upon recognizing a proper sequence of user commands, the SM reaches a state that is determined by the setting of the bistable state circuits, which causes the start of a certain embedded operation by the device. When such an operation has been completed, to resume the initial condition it is possible to use an ENDOP signal (End Operation) generated by the internal circuit that performs the operation to reset the bistable state circuits, and eventually other synchronous circuits that had changed their state upon the recognition of the input sequence.
In certain applications, the reset is done by a very short pulse (of minimum duration), as will be better highlighted below. In other applications, certain state bistable state circuits receive the user clock, other bistable state circuits have their own clock pin coupled to handshake signals with the internal circuits such that upon an internal communication, a bistable state circuit sets. This instantaneously changes the global state of the machine, but the same bistable state circuits must be reset after propagation of the event through a circuit chain. There are also applications in which both reset mechanisms are used in combination.
By considering the interface as a single large finite state machine, it may be observed that in the first type of applications it uses a single (user) clock but a multiple reset, while in the second type of applications it uses a multiple clock (in the sense that different bistable state circuits have different signals on their respective CLK pins).
In the case of applications implementing a hybrid mechanism, there may be state variables with multiple clocks and multiple reset signals. Drawbacks of all these approaches may be summarized as follows.
Wide windows not sensitive to commands. In particular, it must be observed that where a pulse deriving from an internal communication is used to reset the state variables, the pulse must last to ensure reset in all temperature and supply voltage limits. This implies that, during such a reset pulse, eventual user commands will not be accepted, irrespective of their importance.
Complex design. Design complexity increases because in order to cover all possible situations, it is not easy to resolve such a complexity in a few common circuits. On the contrary it is necessary to use a large number of different combination and sequential sub-circuits, whereby each of them must store reset conditions for other sequential circuits that eventually must close the loop by resetting the first ones.
Difficult to reproduce. These structures are specifically designed for solving a particular problem so that when a new device compliant to a different specification is needed, the design must be completely overhauled.
Area occupation. The difficulty of solving the circuit complexity with a standard structure using a single clock and a single reset severely hinders optimization during the phase of automatic synthesis. Basically, while in a standard structure it could be possible to obtain a four flip-flop synthesis requiring about ten memory elements based upon the circuitry according to the above mentioned known approaches. The greater the number of states to be managed, the greater is this proliferation effect.
Difficult to test. If the whole interface could summarize its current state on a bus of state variables of a few bits concentrated in a common area, it would be easy, in a test mode, to force a state, let the structure evolve, and read the state in which the structure evolves after an evaluation. The above discussed approaches, because of their inherent complexity, are difficult to test.
Any tutorial documents pertaining to digital designs invariably stress that for synchronous structures, the design approaches to be followed are the ones leading to the maximum uniformity of the clock and the reset of all bistable state circuits. On the other hand, the above mentioned specifications are satisfied with great difficulty by following such design approaches, as the circuit structures of known commercial devices amply demonstrate.